AArch64 EL2 hypervisor for QEMU virt that boots at EL2
Refine GIC virtual interrupt state reconciliation
author
vm.fail
date
(May 24, 2026, 11:05 AM UTC)
commit
8206b8fd
8206b8fdb9580f95ac5cf53d11d405cd737718f7
parent
f74abf85
f74abf8568ce461047744d27b8edd4f29aedf956
vm.fail
date
(May 24, 2026, 11:05 AM UTC)
commit
8206b8fd
8206b8fdb9580f95ac5cf53d11d405cd737718f7
parent
f74abf85
f74abf8568ce461047744d27b8edd4f29aedf956
+7
-3
+7
-3
drivers/gicv3.c
+7
-3
drivers/gicv3.c
···
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#define GICR_WAKER 0x0014u
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#define GICR_WAKER_PROCESSOR_SLEEP (1u << 1)
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#define GICR_WAKER_CHILDREN_ASLEEP (1u << 2)
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+
#define ICH_LR_STATE(lr) (((lr) >> 62u) & 0x3u)
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#define ICH_LR_INTID(lr) ((uint32_t)((lr) & 0xffffffffu))
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static uintptr_t gicd(uint32_t off)
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{
···
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uint64_t lr;
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uint64_t state;
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-
if (vcpu == (struct vcpu *)0 || vcpu->active_virtual_irq == 0u) {
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+
if (vcpu == (struct vcpu *)0) {
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return;
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}
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__asm__ volatile("mrs %0, ICH_LR0_EL2" : "=r"(lr));
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-
state = (lr >> 62u) & 0x3u;
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-
if (state == 0u) {
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+
state = ICH_LR_STATE(lr);
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if (state == 0u && vcpu->active_virtual_irq != 0u) {
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vcpu_clear_pending_irq(vcpu, (uint32_t)vcpu->active_virtual_irq);
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vcpu->active_virtual_irq = 0u;
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vcpu->stats.virtual_irqs_completed++;
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+
} else if (state != 0u) {
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vcpu->active_virtual_irq = ICH_LR_INTID(lr);
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}
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}
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