AArch64 EL2 hypervisor for QEMU virt that boots at EL2
Use translation table alignment invariants at runtime
author
vm.fail
date
(May 18, 2026, 2:26 PM UTC)
commit
a8b8f2ca
a8b8f2caad5e67fadfd0b989ada99fb3b7f148f8
parent
21d3db6e
21d3db6e70883422eedd60bdc881cdc0857a5047
vm.fail
date
(May 18, 2026, 2:26 PM UTC)
commit
a8b8f2ca
a8b8f2caad5e67fadfd0b989ada99fb3b7f148f8
parent
21d3db6e
21d3db6e70883422eedd60bdc881cdc0857a5047
+15
-1
+15
-1
mm/stage2.c
+15
-1
mm/stage2.c
···
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return addr & 0x0000fffffffff000ull;
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}
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+
static bool table_arena_aligned(void)
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{
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if (!hv_is_aligned_u64((uint64_t)(uintptr_t)g_l1, 65536u)) {
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return false;
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}
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for (uint32_t i = 0; i < HV_ARRAY_SIZE(g_l2_tables); i++) {
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if (!hv_is_aligned_u64((uint64_t)(uintptr_t)g_l2_tables[i], CONFIG_PAGE_SIZE)) {
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return false;
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}
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}
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return true;
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}
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+
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void stage2_init(void)
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{
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BUG_ON(!table_arena_aligned());
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hv_memset(g_l1, 0, sizeof(g_l1));
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hv_memset(g_l2_tables, 0, sizeof(g_l2_tables));
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g_l2_used = 0;
···
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bool stage2_selftest(void)
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{
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-
if (!hv_is_aligned_u64((uint64_t)(uintptr_t)g_l1, 65536u)) {
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if (!table_arena_aligned()) {
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return false;
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}
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for (uint32_t i = 0; i < S2_ENTRIES; i++) {