AArch64 EL2 hypervisor for QEMU virt that boots at EL2
Harden EL1 context serialisation across vCPU exits
author
vm.fail
date
(May 14, 2026, 9:46 AM UTC)
commit
eb9c0745
eb9c0745fda8059b539bd6d4bf0809a3df65339e
parent
616d8df5
616d8df59d8a2a7f4cec7639e29f0923cb14c001
vm.fail
date
(May 14, 2026, 9:46 AM UTC)
commit
eb9c0745
eb9c0745fda8059b539bd6d4bf0809a3df65339e
parent
616d8df5
616d8df59d8a2a7f4cec7639e29f0923cb14c001
+35
+2
core/selftest.c
+2
core/selftest.c
···
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#include "hv/selftest.h"
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#include "hv/stage2.h"
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#include "hv/sysreg.h"
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#include "hv/vcpu.h"
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static void require(bool ok, const char *name)
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{
···
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"selftest guest memory bounds");
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require(policy_selftest(), "selftest policy table");
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require(sysreg_selftest(), "selftest sysreg decoder");
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require(vcpu_frame_selftest(), "selftest vcpu frame serialisation");
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require(log_selftest(), "selftest log wraparound");
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require(allocator_selftest(), "selftest allocator");
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+32
core/vcpu.c
+32
core/vcpu.c
···
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}
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uart_puts("\n");
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}
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bool vcpu_frame_selftest(void)
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{
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struct trap_frame frame;
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struct trap_frame out;
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struct vcpu vcpu;
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hv_memset(&frame, 0, sizeof(frame));
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hv_memset(&out, 0, sizeof(out));
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hv_memset(&vcpu, 0, sizeof(vcpu));
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for (uint32_t i = 0; i < 31u; i++) {
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frame.x[i] = 0x1000u + i;
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}
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frame.sp_el0 = 0x2000u;
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frame.sp_el1 = 0x3000u;
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frame.elr_el2 = 0x4000u;
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frame.spsr_el2 = 0x3c5u;
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frame.esr_el2 = 0x96000000u;
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frame.far_el2 = 0x5000u;
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frame.hpfar_el2 = 0x6000u;
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vcpu_load_frame(&vcpu, &frame);
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vcpu_store_frame(&vcpu, &out);
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return hv_memcmp(frame.x, out.x, sizeof(frame.x)) == 0 &&
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frame.sp_el0 == out.sp_el0 &&
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frame.sp_el1 == out.sp_el1 &&
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frame.elr_el2 == out.elr_el2 &&
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frame.spsr_el2 == out.spsr_el2 &&
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vcpu.last_esr == frame.esr_el2 &&
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vcpu.last_far == frame.far_el2 &&
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vcpu.last_hpfar == frame.hpfar_el2;
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}